This invention relates to fabricating an electromechanical system and a complementary metal oxide semiconductor (CMOS) device on a silicon-on-insulator (SOI) substrate. More particularly, the present invention relates to a method for fabricating an integrated semiconductor device with a barrier layer, and a semiconductor device structure including a barrier layer to separate the electromechanical system from the CMOS device.
The integration of electromechanical and CMOS integrated circuits is being pursued for a variety of applications. For example, nanoelectromechanical systems (NEMS) may form part of a resonant transducer and signal processor by serving as a passive filter or mixing element. NEMS devices are suitable for silicon-on-insulator (SOI) technology, which also corresponds well to integration with CMOS devices.
In order to achieve integration with SOI electromechanical systems and CMOS devices, several challenges need to be overcome. An electromechanical structure may require some freedom of mechanical movement that entails releasing the structure from an underlying layer, such as a buried oxide (BOX) layer. Mechanical movement may involve simple resonation of a device or the translation of mechanical components. In conjunction, the CMOS device may need to be passivated in a dielectric layer as used in many standard interconnect schemes.
Satisfying these discordant design requirements poses a limitation on the integration density with which the electromechanical and CMOS devices may be situated. For example, 500 nm of isotropic etching is needed to release an electromechanical system structure, which translates to about 250 nm of separation between the CMOS device and the electromechanical system device, if the electromechanical system structure can be released from two sides. If the electromechanical system structure can only be released from one side, 500 nm of etching may be required. Some solutions developed to solve this problem involve the fabrication of the electromechanical system on a separate wafer and then bonding that wafer to the CMOS device, but those solutions experience a similar limitation on integration density.